general description maxim? dg508a and dg509a are monolithic cmosanalog multiplexers (muxes): the dg508a is a single 8-channel (1-of-8) mux, and the dg509a is a differen- tial 4-channel (2-of-8) mux. both devices guarantee break-before-make switching. maxim guarantees these muxes will not latch up if the power supplies are turned off with the input signals still present. maxim also guarantees continuous operation when these devices are powered by supplies ranging from ?.5v to ?8v. the dg508a/dg509a are plug-in upgrades for the industry-standard dg508a/dg509a, respectively. maxim? parts have faster enable switching times and significantly lower leakage currents. the dg508a/ dg509a also consume significantly lower power, mak- ing them ideal for portable equipment. applications control systemsdata logging systems aircraft heads-up displays data-acquisition systems signal routing features ? improved second source ? operate from ?.5v to ?8v supplies ? symmetrical, bidirectional operation ? logic and enable inputs, ttl and cmos compatible ? latchup-proof construction ? monolithic, low-power cmos design dg508a/dg509a monolithic cmos analog multiplexers ________________________________________________________________ maxim integrated products 1 ordering information s1 -15v d analog output (inputs) a0 a1 a2 en s2 v+ v- gnd analog input (outputs) +15v +15v enable in (mux on/off control) clock in n.c. n.c. b in q b q c q d q a v+ a in r01 r02 gnd s3s4 s5 s6 s7 s8 -15v dg508a typical operating circuits 19-0028; rev 4; 5/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. devices are available in a lead(pb)-free/rohs-compliant pack- age (except cerdip). specify lead-free by adding a plus (+) to the part number when ordering. * contact factory for dice specifications. part temp range pin-package dg508a cj 0c to +70c 16 plastic dip dg508acwe 0c to +70c 16 wide so dg508ac/d 0c to +70c dice* dg508abk -20c to +85c 16 cerdip dg508adj -40c to +85c 16 plastic dip dg508ady -40c to +85c 16 narrow so dg508aewe -40c to +85c 16 wide so dg508aak -55c to +125c 16 cerdip dg508amy/pr -55c to +125c 16 narrow so dg509a cj 0c to +70c 16 plastic dip dg509acwe 0c to +70c 16 wide so dg509ac/d 0c to +70c dice* dg509abk -20c to +85c 16 cerdip dg509adj -40c to +85c 16 plastic dip dg509ady -40c to +85c 16 narrow so dg509aewe -40c to +85c 16 wide so dg509aak -55c to +125c 16 cerdip dg509amy/pr -55c to +125c 16 narrow so 8-channel sequential mux/demux typical operating circuits continued at end of data sheet. downloaded from: http:///
monolithic cmos analog multiplexers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v+ = 15v, v- = -15v, v gnd = 0v, t a = +25? , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage referenced to v- v+ .....................................................................................+44v gnd ................................................................................. +25v digital inputs, v s and v d (note 1)...................-2v to (v+ + 2v) or 20ma, whichever occurs first current (any terminal, except s or d) .................................30ma continuous current, s or d .................................................20ma peak current, s or d (pulsed at 1ms, 10% duty cycle max) ..40ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ...........842mw narrow so (derate 8.70mwi? above +70?) .............696mw wide so (derate 9.52mw/? above +70?).................762mw cerdip (derate 10.00mw/? above +70?) ................800mw operating temperature ranges: dg50_acj/cwe ..................................................0? to +70? dg50_abk........................................................-20? to +85? dg50_adj/dy/ewe..........................................-40? to +85? dg50_aak/my ...............................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) pdip, wide so, narrow so, cerdip containing lead(pb) ..+240? pdip, wide so, narrow so lead(pb)-free ....................+260? dg508a/dg509a note 1: signals on s_ or d_ exceeding v+ or v- are clamped by internal diodes. limit forward-diode current to maximum current ratings dg508aa/m dg509aa/m dg508ad/e/b/c dg509ad/e/b/c parameter smbol conditions min tp max min tp max units switch analog signal v analog -15 +15 -15 +15 v v d = 10v, i s = -200a 170 400 170 450 drain-source on- resistance r ds(on) sequence each switch on, v a_l = 0.8v, v a_h = 2.4v (note 4) v d = -10v, i s = 200a 130 400 130 450 greatest change in drain-source on-resistance between channels r ds(on) r ds(on) = r ds(on) max r ds(on) min r ds(on) -10v v s 10v 6 6 % v s = 10v, v d = -10v 0.002 0.5 0.002 1 source off- leakage current i s(off) v en = 0v v s = -10v, v d = 10v -0.5 -0.005 -1 -0.005 na v d = 10v, v s = -10v 0.01 2 0.01 5 dg508a v d = -10v, v s = 10v -2 -0.015 -5 -0.015 v d = 10v, v s = -10v 0.005 2 0.005 5 drain off- leakage current dg509a i d(off) v en = 0v v d = -10v, v s = 10v -2 -0.008 -5 -0.008 na v s(all) = v d = 10v 0.015 2 0.015 5 dg508a v s(all) = v d = -10v -2 -0.03 -5 -0.03 v s(all) = v d = 10v 0.007 2 0.007 5 drain on- leakage current dg509a i d(on) sequence each switch on, v a_l = 0.8v v a_h = 2.4v (note 2) v s(all) = v d = -10v -2 -0.015 -5 -0.015 na downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers _______________________________________________________________________________________ 3 electrical characteristics (continued)(v+ = 15v, v- = -15v, v gnd = 0v, t a = +25? , unless otherwise noted.) dg508aa/m dg509aa/m dg508ad/e/b/c dg509ad/e/b/c units parameter smbol conditions min tp max min tp max l o g i c i n p u t v a_ = 2.4v -10 - 10 -0.002 logic input current, input voltage high i ah v a_ = 15v 0.006 10 0.006 10 a v en = 2.4v -10 - 10 -0.002 logic input current, input voltage low i al all v a_ = 0v v en = 0v -10 - -10 -0.002 a dnamic multiplexer switching t transition figure 1 0.6 1. 0 0.6 1. 0 s break-before-make interval t open figure 3 0.2 0.2 s enable turn-on time t on(en) figure 2 0.4 1.0 0.4 1.5 s enable turn-off time t off(en) figure 2 0.2 0.7 0.2 1.0 s off-isolation oirr v en = 0v, r l = 1k , c l = l5pf, v s = 7v rms f = 500khz (note 3) 68 68 db source off-capacitance c s(off) v s = 0v, v en = 0v, f = 140khz 5 5 pf idg508a 25 25 drain off- capacitanc e dgs09a c d(off) v s = 0v, v en = 0v, f = 140khz 12 12 pf suppl positive supply current i+ v en = 2.4v, all v a_ = 0v or 2.4v 0.02 0.2 0.02 0.2 ma negative supply current i- v en = 2.4v, all v a_ = 0v or 2.4v -0.1 -0.01 -0.1 -0.01 ma positive supply current in standby i+ v en = 0v, all v a_ = 0v or 2.4v 0.02 0.2 0.02 0.2 ma negative supply current in standby i- v en = 0v, all v a_ = 0v or 2.4v -0.1 -0.01 -0.1 -0.01 ma power-supply range for continuous operation v-, v+ (notes 4, 5) 4.5 18.0 4.5 18.0 v downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers 4 _______________________________________________________________________________________ electrical characteristics(v+ = 15v, v gnd = 0v, t a = t min to t max , unless otherwise noted.) note 2: i d(on) is leakage from driver into on switch. note 3: off-isolation = 20logv s = input to off switch, v d = output due to v s . note 4: electrical characteristics (such as on-resistance) change when power supplies other than ?5v are used. note 5: for designs requiring single 5v or dual ?v operation, refer to maxim s improved max338 and max339. minimum operating voltage for dg508ady/my and dg509ady/my is ?v. iv i iv i s d dg508aa/m dg509aa/m dg508ad/e/b/c dg509ad/e/b/c parameter smbol conditions min tp max min tp max units switch analog signal range v analog -15 +15 -15 +15 v v d = 10v, i s = -200a 500 550 drain-source on- resistance r ds(on) sequence each switch on, v a_l = 0.8v, v a_h = 2.4v v d = -10v, i s = 200a 500 550 v s = 10v, v d = -10v +50 +50 source off-leakage current i s(off) v en = 0v v s = -10v, v d = -10v -50 -50 na v d = 10v, v s = -10v +200 +100 dg508a v d = -10v, v s = -10v -200 -200 v d = 10v, v s = -10v +200 +100 drain off- leakage current dg509a i d(off) v en = 0v v d = -10v, v s = -10v -100 -100 na v s(all) = v d = 10v +200 +100 dg508a v s(all) = v d = -10v -200 -100 v s(all) = v d = 10v +100 +100 drain on- leakage current dg509a i d(on) sequence each switch on, v a_l = 0.8v, v a_h = 2.4v (note 2) v s(all) = v d = -10v -100 -100 na logic input v a_ = 2.4v -30 -30 logic input current, input voltage high i ah v a_ = 15v +30 +30 a v en = 2.4v -30 -30 logic input current, input voltage low i al all v a_ = 0v v en = 0v -30 -30 a downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers _______________________________________________________________________________________ 5 pin dg508a dg509a dip/so dip/so name function 1, 15, 16 a0, a2, a1 address input 1, 16 a0, a1 address input 2 2 en enable 3 3 v- negative-supply voltage input 4C7 s1Cs4 analog inputs, bidirectional 4C7 s1aCs4a analog inputs, bidirectional 8 d analog outputs, bidirectional 8, 9 da, db analog outputs, bidirectional 9C12 s8Cs5 analog inputs, bidirectional 10C13 s4bCs1b analog inputs, bidirectional 13 14 v+ positive-supply voltage input 14 15 gnd ground pin descriptions 1615 14 13 12 11 10 9 12 34 5 6 7 8 a0 a1a2 gnd v+ s5 s6 s7 s8 top view dg508a en v- s3 s1s2 s4 d 1615 14 13 12 11 10 9 12 34 5 6 7 8 a0 a1gnd v+ s1b s2b s3b s4b db dg509a dip/so en v- s3a s1as2a s4a da pin configurations functional diagrams v+ d a2 a1 a0 en v- gnd s1s2 s3 s4 s5 s6 s7 s8 dg508a cmos decode logic dg508a 8-channel single ended multiplexer v+ da a1 a0 en v- gnd db s1as2a s3a s4a s1b s2b s3b s4b dg509a cmos decode logic dg509a differential 4-channel multiplexer downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers 6 _______________________________________________________________________________________ dg508a en s1 10v switchoutput v d 35pf 1m s2?7 s8 d +2.4v +15v a0a1 a2 gnd -15v 50 logic input v- v+ dg509a en s1 10v switchoutput v ds 35pf 1m s1a?4a, da, s2b, s3b s4b db +2.4v +15v a0a1 gnd -15v 50 logic input v- v+ figure 1a. switching-time test circuit dg508a en v+ s1 -5v switchoutput v d 35pf 1k s2?7 d +15v a0a1 a2 gnd -15v 50 logic input v- figure 2a. dg508a enable-time test circuit dg509a en v+ s1b -5v switchoutput v ds 35pf 1k s1a?4a, da, s2b, s3b db +15v a0a1 gnd -15v 50 logic input v- figure 2b. dg509a enable-time test circuit figure 1b. switching-time test circuit downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers _______________________________________________________________________________________ 7 dg508adg509a en +5v switchoutput v d 35pf 1k all s and da db, d +2.4v +15v a0, a1, (a2) gnd -15v 50 logic input v- figure 3. break-before-make test circuit t open t transition t transition t off (en) t on (en) s 8 on 3v logic input t r < 20ns t f < 20ns switch output v d (see fig. 1) transition time switch output v d (see fig. 2) tenable t (on) t (off) time switch output v d (see fig. 3) open time (b.b.m interval) 50% 0 v s1 v s8 0.8v s1 v 0 v s v s 50% 0v 0.9v 0 0.1v 0 0.8v s8 00 s 1 on figure 4. timing diagram for figures 1, 2, and 3 table 1a. dg508a truth table a2 a1 a0 en on switch x x x 0 none 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 table 1b. dg509a truth table a1 a0 en on switch x x 0 none 0011 0112 1013 1114 x = don t care. x = don t care. downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers 8 _______________________________________________________________________________________ s1a -15v db differentialanalog outputs (inputs) a0 a1 en s2a v+ v- gnd differential analog inputs (outputs) +15v differential 4-channel sequential mux/demux clock in reset enable n.c. j k q clear gnd s3as4a s1b s2b s3b s4b da -15v clock clock dg509a 1/2mm747c73 q j k q 1/2mm747c73 q typical operating circuits (continued) package type package code document no. 16 plastic dip p16-1 21-0043 16 wide so w16-2 21-0042 16 narrow so s16-5 21-0041 16 cerdip j16-3 21-0045 package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
dg508a/dg509a monolithic cmos analog multiplexers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed updated the drain-source on-resistance parameter for both the t a = +25c and t a = t min to t max conditions. 2, 4 deleted the qfn package from the ordering information , absolute maimum ratings , pin configurations , pin descriptions , and package information sections. 1, 2, 5, 8 4 5/10 added the dg508amy/pr and dg509amy/pr parts to the ordering information table. 1 downloaded from: http:///
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